Digital processors access (read from and write to) external memory in a particular time interval based upon the length of the processor cycle required to perform the access. In the case of a microprocessor performing a memory read operation, for example, five states (or clock cycles) of the microprocessor might be required to access the memory.
In such a case, one or more of the states is required to allow the memory device time to place the requested data on the data lines to the microprocessor. If this time is more than the time for one state (clock cycle time), the memory requires more than one state to accomplish this function.
Depending upon the microprocessor clock frequency and the access time of the memory device involved in the memory "read" operation, a greater or lesser number of states is required to access the memory. Ideally, for a given microprocessor clock speed, the memory which is to be accessed by the microprocessor will have been selected to permit memory access in a minimum number of states of the microprocessor.
Often, the microprocessor is required to interface with memory, or other peripheral devices, having access times of different durations. Once the number of microprocessor cycles for a memory access is selected, the maximum access time possible for a memory device is substantially established by the microprocessor clock rate. If slower-access-time memory devices are interfaced with the microprocessor, and if no other adjustments are made, the clock frequency must be slowed to accommodate the slowest attached device.
An alternative, to maintain the microprocessor clock speed, is to introduce additional wait states within the memory access cycle of the microprocessor for slow devices. During these wait states, the microprocessor waits for the memory device to complete its operation. To do this, normally a signal line is coupled from the memory device or its associated controller to the microprocessor; and the microprocessor adds inactive wait cycles until it receives a signal that the data requested from the memory device is available to be read.
In a situation where, for example, two peripheral devices having different access times are interfaced to a microprocessor, it may be desired to maintain a fast clock speed, compatible with the faster (shorter access time) device and yet not introduce wait states into the microprocessor access cycle when accessing the slower device. In some cases, the microprocessor might be incapable of adding wait states during a device access cycle.
This invention permits the use of a digital processor with peripheral devices having variable access times without slowing the basic clock frequency of the microprocessor or introducing microprocessor wait states.